Technical Field
The present disclosure relates to an integrated circuit protected from short circuits caused by silicide, and to a method of fabricating such an integrated circuit.
Detailed Description
FIG. 1 is a cross-sectional view of an integrated circuit IC comprising a pair of memory cells C1, C2. Each memory cell C1, C2 comprises a floating gate transistor FGT1, FGT2 and a selection transistor ST1, ST2 respectively in series. The integrated circuit is formed in/on a substrate comprising a P-type doped well PW of a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer NISO that surrounds the entire well.
A trench 1 extends from the surface of the well PW to the isolation layer NISO. The sidewalls and bottom of the trench 1 are covered by an isolating layer 2 (such as oxide) and the remaining volume of the trench is filled with a semiconductor material 3, such as polycrystalline silicon or “polysilicon”. Together, the trench 1, isolating layer 2, and conductive material 3 form a trench conductor CT.
The floating gate transistors FGT1, FGT2 are formed on opposite sides of the trench conductor CT, on the surface of the substrate. Each floating gate transistor comprises a first doped region R1, a second doped region R2, a horizontal channel CH1, a transistor gate structure TGS, and spacers SP1, SP2.
Regions R1, R2 are N-type doped and respectively comprise shallow lightly doped portions n1, n2 and deeper higher doped portions n1′, n2′ respectively. The first region R1 extends in the well PW from a first edge E1 of the transistor gate structure to the upper edge of the trench conductor CT, and forms the transistor source region (S). The second region R2 extends in the well PW from a second edge E2, opposite the first, of the transistor gate structure to an edge of a transistor gate structure of an adjacent memory cell (not shown), and forms the transistor drain region (D). The channel CH1 extends in the well PW between the regions R1, R2 and has a length L1.
The transistor gate structure TGS is formed above the channel CH1 and comprises a stack of a first oxide layer O1 (tunnel oxide), a first polycrystalline silicon layer P1 (floating gate FG), a second oxide layer O2 (gate oxide), and a second polycrystalline layer P2 (control gate CG). The first spacer SP1 is formed on the first edge E1 of the gate structure TGS above the first doped region R1, and the second spacer SP2 is formed on the second edge E2 of the gate structure above the second doped region R2.
The selection transistors ST1, ST2 each comprise the first doped region R1, a third doped region R3, the trench conductor CT, and a vertical channel CH2. The region R3 is N-type doped and formed in the layer NISO. Regions R1, R3 respectively form the transistor drain (D) and source (S) regions of the selection transistors. The semiconductor material 3 of the trench conductor CT forms a “buried” or “vertical” select gate SG that is common to both selection transistors ST1, ST2, with the isolating layer 2 forming a gate oxide. The channels CH2 extend in the well PW between the regions R1, R3, on opposite sides of the trench conductor CT, and have a length L2.
Silicides SI are formed on the top surfaces of the doped regions R1, R2, the semiconductor material 3 of the trench conductor CT, and the control gates CG. A dielectric isolating material (not shown for the sake of clarity) covers the memory cells C1, C2. The doped regions R2 of transistors FGT1, FGT2 are coupled to a metal track M1 formed in a first metal layer or “metal1” by means of a contact CN traversing the dielectric isolating material.
The metal track M1 serves as a bitline, the layer NISO serves as a source line, and the trench conductor CT serves as a wordline. Another contact (not shown) may be made to the semiconductor material 3 of the trench conductor for the application of wordline voltages. Additional pairs of memory cells extend to the left and the right of the figure, and are coupled to the same bitline and to different wordlines.
Shallow trench isolations or STI (not shown) may be formed parallel to the plane of the figure, on opposite sides of the memory cells. These isolations separate columns of memory cells linked to adjacent bitlines. Each memory cell C1, C2 thus has a width (not shown) defined by the width of the doped regions plus two times half the distance of each shallow trench isolation.
Each memory cell C1, C2 has a length defined by distances D1 to D5. Distance D1 corresponds to the distance from the first edge E1 of the transistor gate structure TGS to the upper edge of the trench conductor CT, distance D2 corresponds to the distance from the second edge E2 of the transistor gate structure TGS to the edge of the contact CN, distance D3 corresponds to half the width of the trench conductor CT, distance D4 corresponds to the length of the transistor gate structure TGS from edge to edge, and distance D5 corresponds to half the width of the contact CN.
As a numerical example, for a semiconductor fabrication technology of 90 nm, distances D1=D2=75 nm, D3=75 nm, D4=100 nm, and D5=45 nm for a total cell length of 370 nm. The width of each cell is equal to 260 nm, for a total cell size of 0.96 micrometers squared.
A memory cell comprising a buried vertical gate thus provides a smaller surface area as compared to a conventional memory cell, wherein both the floating gate transistor and the selection transistor are formed on the surface of the substrate for a cell length of 715 nanometers. For a same width of 260 nm, the cell size is 0.18 micrometers squared for the same semiconductor fabrication technology.
Silicidation is commonly performed by a “self-aligned” silicide or “salicide” process in order to reduce resistance of the silicided areas R1, R2, CG, CT. Nevertheless, there is a high risk that a silicide short circuit or “bridge” will form above the isolating layer 2 between the doped regions R1 and the semiconductor material 3, in the encircled zones. This risk mainly arises due to the thin dimension, for example 10 nm or less, of the isolating layer 2. Such a silicide short disrupts the operation of the memory cell.
One solution to prevent such silicide shorts is to mask the doped region R1 and the semiconductor material 3, such that no silicide forms on these surfaces. Consequently, only the doped regions R2 and the control gates CG are silicided. Nevertheless, this method requires an additional mask and processing steps, and leaves the doped region R1 and the semiconductor material 3 un-silicided. Accordingly, contacts cannot be made to the trench conductor CT between the memory cells C1, C2 and must be placed at the exterior of an array of memory cells. Further, the resistance of the semiconductor material 3 is greatly increased, such that the total length of the trench conductor is reduced.
Another solution is to form a silicidation protection feature covering only the encircled zone of the junction between the doped region R1, the isolating layer 2, and the semiconductor material 3. However, this method also requires additional masks and processing steps, and may be difficult to implement due to minimum feature sizes and proper alignment.
Yet another solution is to silicide the top surface of the semiconductor material 3 before forming the floating gate transistors. Nevertheless, the silicidation process is generally performed during the “back end of line” processing, once the transistors have been completed, in order to avoid contamination of the transistors.